In telecommunication systems, the receiver is assumed to be able to generate a set of local clock signals whose characteristics are identical to the characteristics of the signalling alphabet in use at the transmitter. The alignment of the locally generated clock signals with the clock information extracted from the received signal is often critical in the process of making maximum likelihood symbol decisions. In such situations, a synchronization reference is selected in relation to the modulation protocol employed and extracted from the incoming signal to allow the receiver to keep the frequency or phase of the locally generated clock signals in synchronism with that of the received signal. Examples of synchronization references include the received carrier, the beginning of a frame or the beginning of a symbol of the incoming signal.
Systems using coherent modulation techniques to extract information from the received signal typically use the carrier of the received signal as a synchronization reference because the information transmitted is contained in the phase of the received signal. Carrier synchronization is obtained by aligning the frequency and phase characteristics of the clock signals generated at the receiver to those of the received carrier and is typically accomplished with a PLL (phase locked loop). The PLL achieves frequency and phase synchronism with an input signal by keeping track of the input signal phase to produce an output signal of the same frequency as that of the input signal but with a constant 90.degree. phase offset. The main components of a PLL include a phase detector, a loop filter and a VCXO (voltage controlled crystal oscillator).
The high frequency of a carrier used in telecommunication systems makes the APLL (analog phase locked loop) well suited for carrier synchronization. The APLL usually has a bandwidth large enough to accommodate fast frequency transients in the carrier information extracted from the input signal therefore providing for a faster lock-state acquisition process.
In contrast to coherent systems, systems using non-coherent modulation techniques to extract information from the received signal typically use the beginning of a frame or the beginning of a symbol of the incoming signal as a synchronization reference.
For symbol synchronization, the replica generated at the receiver is a square wave at the symbol transition rate. The symbol rate is much lower than the carrier rate reproduced at the receiver in a system using coherent modulation techniques because each symbol period typically contains a large number of carrier cycles. Similarly, frame synchronization which involves creating a square wave at the frame rate also features a signal of a lower frequency than that of the carrier signal as a frame usually carries a multiplicity of symbols. The square ware created is characterized by zero-crossings coincident with the transitions from one frame to the next.
Frame and symbol synchronization are operated at the receiver on a low frequency synchronization reference and therefore do not necessitate fast lock-state acquisition. They are usually implemented with another type of PLL circuit which is referred to as a DPLL (digital phase locked loop). The DPLL is better suited for low frequency applications because its narrower bandwidth provides a better resolution and accuracy of the output signal characteristics. The DPLL also alleviates some of the problems associated with the APLL, such as for example the sensitivity to dc-drift and the need for calibration and periodic adjustment.
Current DPLLs typically use microcomputers, EEPROM (electrically erasable programmable read-only memory) units and include a DPD (digital phase detector) and a high resolution DAC (digital-to-analog converter) for controlling the VCXO.
Generally, the use of currently available DACs in DPLL designs necessitates the use of a TCVCXO (temperature compensated voltage controlled crystal oscillator). This special type of oscillator is expensive and must be manufactured with a relatively high frequency of oscillation for providing a telecommunication terminal with a wide range of clock signals derived from the output without having to use additional PLLs. However, this high frequency design makes the oscillator more expensive.
The temperature drift is yet another handicap of DAC-based designs that must be compensated. Also, current DAC configurations often present an unsatisfactory control of the phase drift which, as a result, may build-up. These limitations demand additional and expensive circuitry for improving the performance of the DPLL.
The cost of communication systems further increases according to the level of synchronization required in a terminal and mostly in the area of acquisition and tracking loops which often times involve not only hardware, but also software costs. As well, additional costs lie in the extra time required to achieve synchronization before commencing communications, in the energy expended by the transmitter on signals to be used at the receiver as acquisition of tracking aids. These costs increase for example with the transmission rate and the number of transmission channels where improved performance and versatility are necessary.
Accordingly, there is a need for a circuit and method for converting digital energy into high resolution analog control voltages which is simple to implement, cost-efficient and applicable to a variety of telecommunication systems.
The diversity of functionality requirements of current communications systems providing synchronizing capabilities with a synchronization reference operating at various frequencies do not permit an efficient allocation of the resources present at the receiver. As noted above, synchronization references operating at high frequencies necessitate the use of an APLL synchronizer whereas the DPLL can only accommodate low frequency synchronization references. Furthermore, the use of multiple synchronization references which operate at different frequencies makes it desirable for a communication system to provide synchronizing means which can accommodate multiple synchronization references operating at various frequencies.
As such, it is known to provide a telecommunication terminal with synchronization means which can accommodate clock signals operating at various frequencies for synchronization of a receiver and transmitter.